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| MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES6222/D Rev 1, 11/2002 Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer The Motorola MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. MC100ES6222 LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER Freescale Semiconductor, Inc... * * * * * * * Features 15 differential ECL/PECL outputs (4 output banks) 2 selectable differential ECL/PECL inputs Selectable /1 or /2 frequency divider 130 ps maximum device skew Supports DC to 3 GHz input frequency Single 3.3V, -3.3V, 2.5V or -2.5V supply TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics * Supports industrial temperature range * Pin and function compatible to the MC100EP222 Functional Description The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or /2 of the input frequency. The FSELA, FSELB, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the /2 outputs. For the functionality of the MR control input, see Figure 5. , "Functional Diagram," on page 7. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6222 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6222 supports positive (PECL) and negative (ECL) supplies. The MC100ES6222 is pin and function compatible to the MC100EP222. (c) Motorola, Inc. 2002 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MC100ES6222 FSELA QA0 VCC VEE 0 VCC VCC NC CLK0 CLK0 1 VEE VCC 0 1 /1 /2 QB0 0 QB1 1 QB2 VCC QB2 QB2 QB1 QB1 QB0 QB0 QC2 QC3 QD0 QD1 QD2 40 41 42 43 44 45 46 47 48 49 50 51 52 39 38 37 36 35 34 33 32 31 30 29 28 27 NC QA1 VCC 26 25 24 23 22 21 QC0 QC0 QC1 QC1 QC2 QC2 QC3 QC3 QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3 QD4 QD4 QD5 QD5 VCC CLK1 CLK1 0 VEE QC0 QC1 MC100ES6222 20 19 18 17 16 15 14 Freescale Semiconductor, Inc... CLK_SEL 1 VCC QA1 QA1 QA0 QA0 VCC VEE FSELB FSELC 0 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 MR VEE 1 CLK_SEL CLK0 CLK0 CLK1 CLK1 VCC FSELC FSELD MR FSELA FSELB VBB QD4 FSELD QD5 VEE VBB Figure 1. MC100ES6222 Logic Diagram Table 1. Function Table Control Pin FSELA (asynchronous) FSELB (asynchronous) FSELC (asynchronous) FSELD (asynchronous) CLK_SEL (asynchronous) MR (asynchronous) 0 /1 /1 /1 /1 CLK0 Active Figure 2. 52-Lead Package Pinout (Top View) 1 /2 /2 /2 /2 CLK1 Reset. QX = L and QX = H. MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS VEE QD3 Freescale Semiconductor, Inc. MC100ES6222 Table 2. Pin Configuration Pin CLK0, CLK0 CLK1, CLK1 FSELA, FSELB, FSELC, FSELD MR CLK_SEL QA[0:1], QA[0:1] QB[0:2], QB[0:2] QC[0:3], QC[0:3] QD[0:5], QD[0:5] I/O Input Input Input Input Input Output Output Output Output Output Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL DC Power supply Power supply Differential reference clock signal input Alternative differential reference clock signal input Selection output frequency divider for bank A, B, C and D Reset Clock reference select input Bank A differential outputs Bank B differential outputs Bank C differential outputs Bank D differential outputs Reference voltage output for single ended ECL or PECL operation Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Description Freescale Semiconductor, Inc... VBB VEEa VCC a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 3. Absolute Maximum Ratingsa Symbol VCC VIN VOUT IIN IOUT TS TFUNC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature Functional temperature range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V mA mA C C Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol VTT MM HBM CDM LU CIN JA, JC JB TJ a. b. Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity Input Capacitance Thermal resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating junction temperatureb (continuous operation) MTBF = 9.1 years 175 2000 TBD 200 4.0 See Table 9, "Thermal Resistance" on page 9 0 110 Min Typ VCC - 2a Max Unit V V V V mA pF C/W Inputs Condition C Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6222 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6222 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. TIMING SOLUTIONS For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6222 Table 5. PECL DC Characteristics (VCC = 2.5V 5% or VCC = 3.3V 5%, VEE = GND, TJ = 0C to +110C) Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0, CLK1, CLK1 (PECL differential signals) VPP VCMR IIN Differential Input Voltagea Differential Cross Point Voltageb Input Currenta 0.1 1.0 1.3 VCC - 0.3 150 V V A Differential operation Differential operation VIN = VIL or VIN = VIH Clock inputs MR, CLK_SEL, FSELA, FSELB, FSELC, FSELD (PECL single ended signals) VIH VIL IIN Input Voltage High Input Voltage Low Input Currentc VCC - 1.165 VCC - 1.810 VCC - 0.880 VCC - 1.475 150 V V A VIN = VIL or VIN = VIH IOH = -30 mAd IOL = -5 mAd PECL clock outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] Freescale Semiconductor, Inc... VOH VOL IEEe Output High Voltage Output Low Voltage VCC - 1.1 VCC - 1.9 VCC - 1.005 VCC - 1.705 VCC - 0.7 VCC - 1.4 V V Supply current and VBB Maximum Quiescent Supply Current without output termination current 96 170 mA VEE pins a. b. c. d. e. VBB Output reference voltage VCC - 1.38 VCC - 1.22 V IBB = 0.4 mA VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Input have internal pullup/pulldown resistors which affect the input current. Equivalent to a termination of 50W to VTT. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT )/Rload + (VOL - V TT )/Rload + IEE. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6222 Table 6. ECL DC Characteristics (VEE = -2.5V 5% or VEE = -3.3V 5%, VCC = GND, TJ = TJ = 0C to +110C) Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0, CLK1, CLK1 (ECL differential signals) VPP VCMR IIN Differential Input Voltagea Differential Cross Point Voltageb Input Currenta 0.1 VEE + 1.0 1.3 -0.3 150 V V A Differential operation Differential operation VIN = VIL or VIN = VIH Clock inputs MR, CLK_SEL, FSELA, FSELB, FSELC, FSELD (PECL single ended signals) VIH VIL IIN Input Voltage High Input Voltage Low Input Currentc -1.165 -1.810 -0.880 -1.475 150 V V A VIN = VIL or VIN = VIH IOH = -30 mAd IOL = -5 mAd ECL clock outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] Freescale Semiconductor, Inc... VOH VOL IEEe Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 1.4 V V Supply current and VBB Maximum Quiescent Supply Current without output termination current 96 170 mA VEE pins a. b. c. d. e. VBB Output reference voltage -1.38 -1.22 V IBB = 0.4 mA VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Input have internal pullup/pulldown resistors which affect the input current. Equivalent to a termination of 50W to VTT. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT )/Rload + (VOL - V TT )/Rload + IEE. TIMING SOLUTIONS For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6222 Table 7. AC Characteristics (ECL: VEE = -3.3V 5% or VEE = -2.5V 5%, VCC = GND) or (PECL: VCC = 3.3V 5% or VCC = 2.5V 5%, VEE = GND, TJ = 0C to +110C)a Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0, CLK1, CLK1 (PECL or ECL differential signals) VPP VCMR fCLK Differential input voltageb (peak-to-peak) Differential input crosspoint voltagec Input Frequency PECL ECL 0.2 1.0 VEE+1.0 0 1.3 VCC - 0.3 -0.3V 2000 V V V MHz Differential ECL/PECL clock outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5] tPD VO(P-P) Propagation Delay CLK0 or CLK1 to Qx MR to Qx fO < 1.0 GHz fO < 2.0 GHz tsk(O) Output-to-output skew within QA[0:1] within QB[0:2] within QC[0:3] within QD[0:5] any output tsk(PP) tJIT(CC) tSK(P) DCO Output-to-output skew (part-to-part) Output cycle-to-cycle jitter Output pulse skewd Output Duty Cycle fREF < 0.1 GHz fREF < 1.0 GHz fREF < 2.0 GHz 49.85 48.50 47.00 5 50 50 50 670 820 970 ps ps mV mV 35 35 50 60 130 300 TBD 15 50.15 51.50 53.00 ps ps ps ps ps ps ps ps % % % DCREF = 50% DCREF = 50% DCREF = 50% Differential Differential Differential Differential output voltage (peak-to-peak) TBD TBD Freescale Semiconductor, Inc... a. b. c. d. tr, tf Output Rise/Fall Time 50 300 ps 20% to 80% AC characteristics apply for parallel output termination of 50 to VTT. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. MOTOROLA For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6222 Differential Pulse Generator Z = 50W ZO = 50 ZO = 50 RT = 50 VTT DUT MC100ES6222 RT = 50 VTT Figure 3. MC100ES6222 AC test reference Freescale Semiconductor, Inc... CLKN CLKN MR QX QX tPD (CLK to Q) 50% tPD (MR to Q) Figure 4. MC100ES6222 tPD measurement waveform APPLICATIONS INFORMATION Asynchronous Reset Functional Diagram CLKN MR QX (/2) QX (/1) Figure 5. Functional diagram TIMING SOLUTIONS For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6222 APPLICATIONS INFORMATION Understanding the junction temperature range of the MC100ES6222 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6222, the MC100ES6222 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this datasheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: Maintaining Lowest Device Skew The MC100ES6222 guarantees low output-to-output bank skew of 130 ps and a part-to-part skew of max. 300 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6222 is a mixed analog/digital product. The differential architecture of the MC100ES6222 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. Freescale Semiconductor, Inc... TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17 C/W (2s2p board, 200 ft/min airflow, see Table 9 on page 9) and a typical power consumption of 1026 mW (all outputs terminated 50 ohms to V TT, V CC =3.3V, frequency independent), the junction temperature of the MC100ES6222 is approximately TA + 17 C, and the minimum ambient temperature in this example case calculates to -17 C (the maximum ambient temperature is 93 C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES6222 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6222 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8. Ambient temperature ranges (Ptot = 1026mW) Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20 C/W 18 C/W 17 C/W 16 C/W 15 C/W TA, mina -21 C -18 C -17 C -16 C -15 C TA, max 89 C 92 C 93 C 94 C 95 C VCC 33...100 nF 0.1 nF VCC MC100ES6222 Figure 6. VCC Power Supply Bypass a. The MC100ES6222 device function is guaranteed from TA=-40 C to TJ=110 C MOTOROLA For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6222 APPLICATIONS INFORMATION Using the thermally enhanced package of the MC100ES6222 The MC100ES6222 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the leadframe is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6222 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6222. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6222 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 7. "Recommended thermal land pattern", providing an efficient heat removal path. all units mm recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. Freescale Semiconductor, Inc... Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Figure 8. Recommended solder mask openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistancea ConvectionLFPM Natural 100 200 400 800 RTHJAb C/W 20 18 17 16 15 RTHJAc C/W 48 47 46 43 41 4e 29f RTHJC C/W RTHJBd C/W 4.8 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 8. "Recommended solder mask openings" shows a recommend solder mask opening with respect to the a. Applicable for a 3 x 3 thermal via array b. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5 c. Junction to ambient, single layer test board, per JESD51-3 d. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 e. Junction to exposed pad f. Junction to top of package It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6222 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. TIMING SOLUTIONS For More Information On This Product, 9 Go to: www.freescale.com I I I IIIIIIIIII IIIIIIII IIII I IIIII II IIIIIIIIII IIIIIIIIII I II II II II II II II II II II II II IIII II II II II II IIII II II II II II IIII II II II I I IIIII II IIII II IIIIIIIII IIIIIIII IIIIIII IIIIIII 0.2 1.0 0.2 4.8 1.0 all units mm 4.8 Exposed pad land pattern I IIIII IIIIIIIIII IIIIIIIIII I IIIII IIIIIIIIII IIIIIIIIII II II IIII I I II II IIII I I II II I I II II IIII I II II IIII I II IIIIIIII I IIIIIIII I IIIIIIIII IIIIIII IIIIIIII IIIIII 16 MOTOROLA Freescale Semiconductor, Inc. MC100ES6222 OUTLINE DIMENSIONS TB SUFFIX PLASTIC LQFP PACKAGE EXPOSED PAD CASE 1336A-01 ISSUE O 4X 4X 13 TIPS 0.2 H A-B D D PIN 1 INDEX 1 52 40 39 0.2 C A-B D 7 1.5 1.3 0.05 B 10 6 12 5 6 6 4 X 4 VIEW AA 0.20 R 0.08 (0.2) 0 MIN 0.20 R 0.08 0.25 GAUGE PLANE A Freescale Semiconductor, Inc... 0.20 0.05 0.75 0.45 (1) 7 0 13 14 26 27 X=A, B OR D 5 6 64 10 6 12 4 C L B B VIEW Y 48X 0.65 H 1.7 MAX 4X (12 ) VIEW AA 52X 8 (0.3) BASE METAL 0.1 C 8 J C SEATING PLANE 52X 0.08 M 0.40 0.22 5 C A-B D 4X (12 ) J PLATING 0.20 0.09 4.78 4.58 4.78 4.58 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. THIS DIMENSION IS MAXIMUM PLASTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. EXPOSED PAD VIEW Y VIEW J-J MOTOROLA For More Information On This Product, 10 Go to: www.freescale.com C EECC CEEE EECC CEEE EECC CEEE CC EEEEE 0.35 0.20 8 SECTION B-B 0.16 0.07 8 TIMING SOLUTIONS Freescale Semiconductor, Inc. MC100ES6222 NOTES Freescale Semiconductor, Inc... TIMING SOLUTIONS For More Information On This Product, 11 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MC100ES6222 Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. E Motorola, Inc. 2001. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA For More Information On This Product, 12 Go to: www.freescale.com MC100ES6222/D TIMING SOLUTIONS |
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